1. Field of the Invention
The invention relates to an apparatus and a method that can perform an interference cancellation, and more particularly to an apparatus and the corresponding method that can perform cancelling of the cross clock domain interference.
2. Description of the Prior Art
In the conventional communication system, interference cancellation during performing the task of cross clock domain usually introduces the Farrow structure to process the interpolating calculation so as to transform corresponding data among different clock domains. In the art, the Farrow structure adopts a relevant polynomial to simplify the complicity of the interpolating calculation. Yet, it is well known that the application of the mathematical polynomial combinations is always lead to an inevitable result of substantial computational errors or bias. It is general to note that the maximum computational error will fall at the point having a 180-degree phase. Also, in the case of meeting the particular inputs and outputs for two close clock domains, the computational error might rise to a degree that the introduction of the Farrow structure seems meaningless. In particular, when the two clock domains are almost the same for the inputs and the outputs, a correct computation to obtain interpolated data having 180-degree phases is extremely impossible from a Farrow-structure scheme.
For example, in the application of HDMI Ethernet channel, due to the feature of bi-direction transmission on a single cable, interference may arise from the incoming signals and the echo of the outgoing signals. In the art, an echo canceller is usually introduced to perform the cancellation of the echoes. For the opposing ends of the HDMI Ethernet channel exist a tiny clock domain error of 0˜200 ppm, data at the transmitter end (Tx) needs to undergo clock domain switching to transform into data having the clock domain of the receiver end (Rx), and then the echo canceller can be applied to the clock domain of the Rx. In this application, if the Farrow structure is introduced to process the clock domain switching, the interpolating accuracy would be poor due to the tiny difference between clock domains of Tx and Rx. Accordingly, for obtaining a satisfied computational precision from the Farrow structuring, a high-order polynomial is inevitable, but trade-off is a large number of taps in the Farrow structure. As a result, the computational complexity is high and the time delay in signaling is usually prolonged.
Further, another disadvantage from using the Farrow structure is the increase of the computational complexity at the echo canceller end. In the HDMI Ethernet channel, if an MLT-s signal emitted from transmitter end Tx has three value levels (0+1 −1), then no clock domain switching is needed, and the echo canceller needs to perform additions only with no need of multiplication operation. However, by involving the Farrow structure for obtaining the interpolated data with different phases and timings, more bits are needed to realize the data of Tx. Definitely, in this situation, it can be foreseen that multiplication operations in the echo canceller is inevitable and the computational complexity thereof may arise comprehensively as well.